[ beautifulsmile @ 12.04.2010. 16:54 ] @
Code: LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY komparator IS PORT ( broj1 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); broj2 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); manji : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); veci : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END komparator; ARCHITECTURE KOMP of komparator IS signal manji_manji : STD_LOGIC_VECTOR (7 DOWNTO 0); signal veci_veci : STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN manji <= manji_manji; veci <= veci_veci; process(broj1,broj2,veci_veci,manji_manji) begin if (broj1<broj2) then manji_manji <= broj1; veci_veci <= broj2; elsif (broj1>broj2) then manji_manji <= broj2; veci_veci <= broj1; else manji_manji <= broj1; veci_veci <= broj1; END if; END process; END KOMP; Moze li neko da mi objasni zasto stalno imam gresku Error (10476): VHDL error at komparator1.vhd(37): type of identifier "manji" does not agree with its usage as "std_ulogic" type?? Hvala unaprijed! |